1. Field of the Invention
The present invention relates to a fabrication method for a non-volatile memory device. More particularly, the present invention relates to a fabrication method for an electrically erasable programmable read only memory device that has a high breakdown voltage.
2. Description of the Related Art
In the conventional non-volatile memory device, which includes the erasable programmable read only memory (EPROM) device, the electrically erasable programmable read only memory (EEPROM) device and the flash memory device, the stored memory or data is retained and is not being erased during the shortage of the power supply. These types of memory devices thus possess a superior information storage characteristic, and the research for the development in this area continues.
An electrically erasable programmable read only memory is one type of the non-volatile memory devices. In general, an EEPROM cell comprises two gates, which includes a floating gate formed with polysilicon for charge storage and a control gate to control the retrieval of information. The floating gate is normally maintained in a "floating" condition and is not connected to any circuitry, whereas the control gate is normally connected to the word line. The EEPROM cell further includes a tunnel oxide layer and a dielectric layer formed between the substrate and the floating gate, and between the floating gate and the control gate, respectively. In addition, source/drain regions are formed in the substrate on both sides of the control gate.
The peripheral high voltage circuit region device, used to connect the EEPROM and the peripheral circuit, requires withstanding a higher voltage when the electrical erasure or the programming process is performed. However, under the current trend of a higher integration, the device dimension is reduced according to the design rule. The device dimension for the peripheral high voltage circuit region decreases correspondingly. Since under a normal high voltage operation, the thickness of the device gate oxide layer for the peripheral high voltage circuit region can not be easily reduced. Similarly, the channel length of the peripheral high voltage circuit region can not be reduced. The difficulty for fabricating an electrically erasable programmable read only memory device is thereby greatly increased.
Furthermore, during the operation of a memory transistor, the higher the gate-coupling ratio between the floating gate and the control gate, the working voltage for an operation is lower. The gate-coupling ratio between the floating gate and the control thus needs to be increased.
Approaches to increase the gate-coupling ratio include increasing the overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the dielectric constant (k) of the dielectric layer between the floating gate and the control gate. The thickness of the dielectric layer between the floating gate and the control gate, however, must maintain a certain thickness to prevent an entry of the electrons trapped in the floating gate into the control gate, leading to an ineffective device. Since increasing the dielectric constant of the dielectric layer between the floating gate and the control gate involves issues such as replacing the processing equipment and the maturity or immaturity of the current technology, the approach of increasing the dielectric constant of the dielectric layer can not be easily achieved.